Vertical MOSFETs are popular as high voltage, high power transistors due to the ability to provide a thick, low dopant concentration drift layer to achieve a high breakdown voltage in the off state. Typically, the MOSFET includes a highly doped N-type substrate, a thick low dopant concentration N-type drift layer, a P-type body layer abutting the drift layer, an N-type source at the top of the body layer, and a gate separated from the body region by a thin gate oxide. It is common to provide a vertical trenched gate. A source electrode is formed on the top surface, and a drain electrode is formed on the bottom surface. When the gate is sufficiently positive with respect to the source, the channel region of the P-type body between the N-type source and the N-type drift layer inverts to create a vertical conductive path between the source and drain.
In the device's off-state, when the gate is shorted to the source or negative, the drift layer depletes and large breakdown voltages, such as exceeding 600 volts, can be sustained between the source and drain. However, due to the required low doping of the thick drift layer, the on-resistance suffers. Increasing the doping of the drift layer reduces the on-resistance but lowers the breakdown voltage.
It is known to form alternating vertical columns of P and N-type silicon, extending to the substrate, instead of a single N-type drift layer, where the charges in the columns are balanced and where the P and N-type columns completely deplete at a high voltage when the MOSFET is off. This is referred to as a super junction. In such a configuration, the dopant concentration of the N-type column can be higher than that of a conventional N-type drift layer. As a result, on-resistance can be reduced for the same breakdown voltage. A super junction MOSFET can be formed by a multiple epitaxial growth and implantation process. Forming thick and alternating P and N-type columns extending to the substrate requires many cycles of epitaxially growing a portion of the column thickness, then masking and implanting the P and N-type dopants, then growing more of the column thickness and repeating the masking and implantation process. The number of implantation steps may exceed twenty, depending on the thickness. Between each implant cycle, the dopants undesirably laterally spread due to the high process temperatures. This greatly increases the required cell pitch in an array of cells, making the die larger. As a result, the MOSFET is not optimally formed and the process is very time-consuming.
Alternatively, a super junction can be formed by etching deep trenches in N-type silicon that are refilled by a P-type epitaxial layer. The trenches must be deep so that there is a sufficiently long vertical drift layer to support a depletion region for a high breakdown voltage. Forming deep trenches is time-consuming and therefore expensive.
Such power MOSFETs are formed to have a large number of identical parallel cells. Any variation between the devices can cause non-uniform currents and temperatures to result across the MOSFET, reducing its efficiency and breakdown voltage.
What is needed is a power MOSFET that does not suffer from the above-described drawbacks and limitations of the prior art.